EN0-001 무료 덤프문제 온라인 액세스

Many ARM cores provide two instruction sets, ARM and Thumb. Which THREE of the following statements apply to the Thumb instruction set implemented for the ARMv7-A architecture? (Choose three)

• A.Thumb is a hybrid 16/32-bit instruction set
• B.Thumb code is always more power-efficient than equivalent ARM code
• C.The Thumb instruction set can access the Advanced SIMD "NEON" instructions
• D.No Thumb instructions can be conditionally executed
• E.Thumb code is always slower than the equivalent ARM code
• F.Some routines take more instructions in Thumb code than in the equivalent ARM code

A message passing system between two CPUs is implemented using data stored in a shared area of memory. To pass a message, the first CPU executes the instructions:

The second CPU receives the message using the instructions:

On both CPUs, r1 = 0x5000 and r2 = 0x6000. At which of the points A, B, C and D must Data Memory Barrier (DMB) instructions be placed in order to ensure messages are passed reliably and efficiently?

• A.A only
• B.C only
• C.A and D
• D.B and C

An advantage of removable flash memory over built-in flash memory is that:

• A.It is quicker to access, providing far greater bandwidth for read operations.
• B.It has a longer life, indicated by being rated for a higher number of write cycles.
• C.Storage can be easily replaced, for example to increase capacity.
• D.It takes up less physical space in a device, and does not require any space on the printed circuit board.

The instruction LDR pc, [ r1 ] takes longer to execute on a particular system, than the instruction LDR r0, [ r1 ]. In both cases, r1 points to the same address in external memory.
Which of the following is the most likely explanation of why it takes more cycles?

• A.The LDR pc, [ r1 ] instruction requires additional alignment checking, as the result must be half word-aligned (Thumb) or word-aligned (ARM)
• B.The value read from address r1 must be passed from the data side of the processor to the instruction side
• C.The LDR pc, [r1] causes the instruction pipeline to be flushed, but the LDR r0, [r1] does not
• D.The LDR r0, [r1] can be speculatively executed, but the LDR pc, [r1] instruction cannot be speculatively executed

Before execution: R0=0xFFFFFFFF
R1 = ?
EOR R0, R0, R1
If R0=0x00000000 after executing the EOR instruction above, what was the value in R1 before the instruction executed?

• A.0x00000000
• B.0xAAAAAAAA
• C.0xFFFFFFFF
• D.0x11111111